On July 13, China's first AI chip using software-defined and 3D near memory computing technology was officially unveiled in Shanghai. This chip has achieved computing power of 520 trillion floating-point operations per second on the 14-nm process. Its biggest feature is that it has embarked on a high-end computing power development path that does not rely on advanced processes through innovation in the underlying architecture. According to information, the chip uses software-defined and three-dimensional vertical stacking technology to closely integrate the computing unit with the storage unit, and the access bandwidth reached 6.4 TB per second, alleviating the “storage wall” bottleneck that has plagued chip design for a long time in terms of architecture. Since it no longer simply relies on process miniaturization to improve performance, the supply chain of this technology route is more stable and controllable. Also released simultaneously is the full-stack software tool chain supporting the chip, which is compatible with mainstream deep learning frameworks, and forms a complete product system from a single accelerator card and AI server to liquid-cooled supernodes and large-scale intelligent computing clusters, which can provide large-scale and implementable computing power support for large-scale model training and inference.
Zhitongcaijing · 3d ago
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On July 13, China's first AI chip using software-defined and 3D near memory computing technology was officially unveiled in Shanghai. This chip has achieved computing power of 520 trillion floating-point operations per second on the 14-nm process. Its biggest feature is that it has embarked on a high-end computing power development path that does not rely on advanced processes through innovation in the underlying architecture. According to information, the chip uses software-defined and three-dimensional vertical stacking technology to closely integrate the computing unit with the storage unit, and the access bandwidth reached 6.4 TB per second, alleviating the “storage wall” bottleneck that has plagued chip design for a long time in terms of architecture. Since it no longer simply relies on process miniaturization to improve performance, the supply chain of this technology route is more stable and controllable. Also released simultaneously is the full-stack software tool chain supporting the chip, which is compatible with mainstream deep learning frameworks, and forms a complete product system from a single accelerator card and AI server to liquid-cooled supernodes and large-scale intelligent computing clusters, which can provide large-scale and implementable computing power support for large-scale model training and inference.
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