Taiwan's Yangming Jiaotong University and TSMC's R&D team have made new progress in the field of two-dimensional semiconductors and proposed an atomic-level interface engineering technology that can reduce the size of transistors while maintaining high electrical performance, which is expected to drive the development of next-generation low-power semiconductor technology. The relevant research results were published in “Nature Electronics”. The research team said that two-dimensional semiconductor materials are only a single atom thick, have excellent electrical properties, and are considered potential materials that exceed the limitations of silicon-based chips. However, when manufacturing transistors, the interface between the ultra-thin insulating layer and the semiconductor is prone to defects, leading to electron scattering, and the improvement of transistor performance faces bottlenecks. By constructing an ultra-thin alumina interface layer on the surface of a single-layer molybdenum disulfide semiconductor and combining it with a high dielectric constant hafnium oxide gate medium, the researchers improved the material interface quality, so that the transistor simultaneously achieved stronger electronic control capabilities and higher carrier migration performance.

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