• Atomera will present DRAM scaling work at SISPAD 2026 in Kumamoto, Japan on Sept. 28, 2026.
• The paper outlines TCAD results supporting 4F² DRAM junctionless vertical-channel transistors using MST-defined substrate doping to meet drive and retention targets.
• A separate SISPAD 2026 poster on Sept. 29, 2026 will cover compact modeling of off-state leakage and breakdown in GaN-on-Si HEMTs.
• The poster compares conventional silicon, high-resistivity silicon, and MST-modified silicon, showing lower low-voltage leakage and delayed high-field current rise with MST.

Disclaimer: This news brief was created by Public Technologies (PUBT) using generative artificial intelligence. While PUBT strives to provide accurate and timely information, this AI-generated content is for informational purposes only and should not be interpreted as financial, investment, or legal advice. Atomera Inc. published the original content used to generate this news brief via Business Wire (Ref. ID: 20260922168955) on September 22, 2026, and is solely responsible for the information contained therein.