The Zhitong Finance App learned that CICC released a research report saying that the core significance of DeepSeek V4.1 Flash is to achieve higher task completion efficiency and unit GPU output at lower calculation, storage, and storage costs through architecture and inference system optimization. Using the optimization logic of V4.1 Flash, the bank saw that the 10T model originally needed to be carried on the NVIDIA Blackwell series 64 card system is expected to be deployed on the 64 card Hopper series system. That is, domestic computing power chips with mainstream performance in 2026-2027 (such as the Shengteng 960 series) are expected to support the continuous expansion of domestic models to 10T-20T parameter numbers platforms, and the closed loop of domestic computing power requirements has been confirmed once again.
CICC's main views are as follows:
Cost reduction: V4.1 Flash is not a simple reduction model, but rather a systematic reduction in repeated computation, storage, and data handling in long-context reasoning
CED splits the 40-layer transformer into a 20-layer encoder and a 20-layer decoder, so that long prompts do not need to completely go through the latter 20 decoders, thereby reducing the amount of Prefill calculation. CSA2 multiplexed Global KV and Top-K through full, Reindex, and Reuse layer division; after superimposing FP4 Main KV and SWA Bounded Replay, Global KV Cache dropped to about 1/4 of V4 Flash, and Persistent KV Cache dropped to about 1/8. At the same time, Single-Pass MHC uses Kernel Fusion to reduce repetitive activation read/write, further reducing HBM bandwidth pressure.
Efficiency gain: V4.1 Flash achieves higher task completion efficiency with lower unit resource consumption through smaller dynamic computation, external memory, and higher Decode throughput
In the Prefill and Decode stages, each token activates only about 8B and 16B parameters; Engram separates some static knowledge from backbone dynamic calculations and retrieves it as needed; and dSpark improves Decode efficiency through lightweight draft, confidence prediction, and dynamic scheduling.
risk
Model price competition risk, hardware supply chain risk, AI commercialization risk.